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Lead Product Engineer (DDR)

5.00 to 7.00 Years   Pune   19 Dec, 2021
Cadence Design
Job LocationPune
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Software
Functional AreaGeneral / Other Software,Testing
EmploymentTypeFull-time

Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

  • Position Requirements
    • M.S. or BTech Electrical/Computer Engineering (or similar degree)
    • Exp 5 years
    • Exposure to DDR Controller and DDR PHY Design, Functional Verification and Silicon bring up
    • Experience in SOC design implementation, from RTL to final GDS.
    • Knowledge of SOC platforms
    • Static timing closure experience.
    • Experience with industry standard DFT flows and methodologies.
    • Experience using advanced mixed signal verification, and system simulation tools.
    • Exposure to all major IC implementation, design, and verification tools.
    • Prior experience with Silicon validation and characterization of DDR subsystems
    • Prior hands-on experience with high-end lab equipment such as Scopes, BERTs, AWGs, temperature controllers, programmable power supplies
    • Prior experience with test automation program development (using C)
    • Prior experience with PCB design, debug and signal integrity will be helpful
    • Good understanding of electrical signaling aspects
    • Strong debug and problem-solving skills
    • Ability to clearly communicate technical challenges.
    • Willing to travel to customer sites worldwide including overseas Travel
    • Strong communications skills
    • Working with global (US, west coast and east coast) teams, which work in different time-zones
  • Position Description (what the role does)
    • Main technical interface for customer pre and post silicon SOC.
    • Work closely with Physical design team and RTL team to understand chip architecture, hierarchy.
    • Perform gate level simulation and RTL simulation to verify functionality.
    • Support customer Pre-post silicon SOC teams from initial DDR integration and bring-up.
    • Assist customer with GLS and timing closure.
    • Drive and support Customer silicon evaluations
    • Post silicon Validation, testing and characterization of cadence internal silicon test-chips
    • Own an in-depth cadence silicon test-chip bring-up, functional validation and PVT characterization
    • Collect structured test measurement data and perform data analysis
    • Develop and execute comprehensive test plan using high-end equipment (scopes, BERTs)
    • Participate in validation and characterization of critical sub-blocks like high-speed IOs, DDR Power management system etc.
    • Develop and optimize comprehensive test automation
    • Participate in collateral development (characterization reports)
    • Update DDR teams with the latest customer feedback and competitive analysis.
    • Work closely with other DDR teams to understand chip architecture, hierarchy and provide feedback on silicon performance, margin to designed specification for helping improve and fine tune IP design
We re doing work that matters. Help us solve what others can t.,

Keyskills :
manual testingautomationcustomer relationsjavajiragate level simulationpcb designmixed signaltiming closurephysical designproblem solvingtest automationpower management

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