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| Job Location | Noida |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Manufacturing |
| Functional Area | Sales / BD |
| EmploymentType | Full-time |
The Incumbent will be responsible for Synthesis, Constraint development and Timing SignOff of products related to Engine control , Safety(including airbag) , Body, Chassis and Advanced Driver Assistance System(ADAS) for futuristic cars.The job involve interactions with RTL/DFT designers to understand system and develop constraints for Synthesis and Implementation. Candidate will be part of the team responsible for Synthesis and Timing signoff for chip level or block while working with Implementation engineer at every stage for getting best QOR through optimum placement , CTS and timing closure for products involving state of the Art technologies like 7nm FINFET and 28FDSOI with high frequency and low power challenges. These SOC involve Integration of analog IPs and are Multi-supply, Multi-mode, Multi-corner having complex multiple clock structures. Constantly challenged to meet the automotive standards along with closing the design requirements., Synthesis and STA Expertise with synopsys/Cadence toolsGood understanding of chip timing constraintsCapable of working independently and problem solvingKnowledge of full RTL to GDSII flow to take timing closure from RTL to signoffShould have good understanding of verilog/VHDLExposure to low power techniquesKnowledge of tcl and perl scripting is a mustShould have a strong sense of urgency.
Keyskills :
timing closureperl scriptingartsocrtlstaperldesigntimingclosurecontrolchassisplacementscriptingsynthesisautomotiveintegrationimplementationtclips